Analog chip runs large Fourier transforms using half a million flash memory cells

Mapping a digital algorithm to physical memory arrays

Fourier transforms break down complex signals into their individual frequencies to uncover hidden patterns in sound, radar and digital imagery, technologies vital for robotics and space exploration. Standard computing systems calculate these signals using the fast Fourier transform, known as the FFT. The mathematical formulation relies on an O(N log N) scaling law, recursively dividing large transforms into smaller pieces to speed up calculations on digital microprocessors. While analog hardware handles data as continuous electrical quantities at lower energy, it previously struggled to run large transforms because the algorithm was tailored for digital logic, according to research published in Nature Electronics.

Analog in-memory computing has gained traction as a low-power accelerator for matrix multiplications, a core operation behind artificial intelligence models. However, mapping the divide-and-conquer strategy of the FFT to analog chips remained an unsolved problem. The team tackled this limitation by combining the recursive breakdown of the algorithm with large physical memory blocks.

“For years, our group and many others have been exploring analog in-memory computing as a very efficient accelerator for matrix multiplications.”

— T. Patrick Xiao, Sandia National Laboratories

Calculating a 65,536-point transform with SONOS flash cells

The researchers stopped the mathematical division of the Fourier transform once the size of the subproblem matched the physical array of the hardware. This hybrid innovation lets the system complete essential matrix calculations in parallel inside the memory array, while digital circuits finish the remaining operations. To test the architecture, the group programmed discrete Fourier transform coefficients directly into SONOS flash memory devices, as reported by TechXplore.

SONOS cells store an electrical charge inside an ultra-thin insulating layer, which retains numerical data without needing continuous power. The team configured a 512 × 1,024 block inside the memory array with a 256-point discrete Fourier transform matrix. By running more than 500,000 flash devices simultaneously, the analog processor successfully completed a 65,536-point FFT without suffering catastrophic signal error accumulation.

Signal processing beyond artificial intelligence workloads

Prior analog implementations had only demonstrated small transforms of up to 64 or 128 points before noise degraded the computation. By controlling the SONOS cells with high precision, the team maintained accurate matrix calculations across half a million components at once. In practical tests, the hybrid platform processed tasks including radar processing, image deblurring and audio filtering, proving that in-memory analog architectures can address workloads well outside routine matrix multiplication for artificial intelligence. As researchers refine the invention, the breakthrough could also pave the way for new patent filings and commercial applications in low-power signal processing.

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